1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having reduced sensing noise and sensing current by decreasing the number of memory cells activated by a word line.
2. Description of the Related Art
FIG. 1 shows a typical configuration of a conventional semiconductor memory device. Referring to FIG. 1, memory cells in a memory cell array 10 are arranged in a matrix form, and sub-word lines 12 and bit lines 14 for selecting memory cells to be accessed are arranged in column and row directions, respectively. A memory cell (not shown) is disposed at an intersection of a sub-word line 12 and a bit line 14.
A sub-word line driver 16 disposed below the memory cell array 10 activates one of the sub-word lines 12 in response to a pre-word line signal PW provided from a pre-word line decoder (not shown). Sense amplifiers (S/As) 18a and 18b disposed at the sides of the memory cell array 10 are connected to the bit lines 14 to read data from memory cells selected by the sub-word line and the bit lines 14. The sub-word line driver 16 drives one of the sub-word lines 12 in response to the pre-word line signal PW which is decoded by the pre-word line decoder (not shown) and a signal PX made from a row address. One of the bit lines 14 connected to the sub-word line 12 driven by the sub-word line driver 16 is selected by a column address. Memory capacity of a semiconductor memory device as shown in FIG. 1 may be increased by extending the memory cell array 10 in the row or column direction.
FIG. 2 shows a configuration of a semiconductor memory device in which a memory cell array is extended in the row direction. Referring to FIG. 2, memory cell groups 20a and 20b each having a size of n.times.n memory cells are arranged in the row direction. Sub-word line drivers 26a and 26b are respectively disposed below the memory cell groups 20a and 20b. Sense amplifiers 28a, 28b and 28c are disposed at the sides of the memory cell groups.
In response to a pre-word line signal PW, a signal PX and group select signals RAi/RAiB which are obtained by decoding a row address, one of the sub-word line drivers 26a and 26b drives one of the sub-word lines 22 in a memory cell group. One of bit lines 24 connected to the driven sub-word line 22 is selected by a column address.
As compared with the memory cell array of FIG. 1, the memory cell array of FIG. 2 has a disadvantage in that an area required for decoding the row address increases. To overcome this problem, a memory cell array as shown in FIG. 3 is employed.
FIG. 3 shows a configuration of a semiconductor memory device in which a memory cell array is extended in a column direction. Referring to FIG. 3, memory cell groups 30a and 30b each having a size of n.times.n memory cells are arranged in the column direction. A sub-word line driver 36 is disposed below the memory cell group 30a. Sense amplifiers 38a and 38b are disposed at the sides of the memory cell groups 30a and 30b. Sub-word lines 32 are commonly used in the memory cell groups 30a and 30b and driven by the sub-word line driver 36. Each sense amplifier 38a is controlled by a sense amplifier control circuit 39.
The sub-word line driver 36 drives one of the sub-word lines 32 in response to a pre-word line signal PW and a signal PX. One of bit lines 34 connected to the driven sub-word line 32 is selected by a column address and group select signals RAi and RAiB. In FIG. 3, the group select signals RAi and RAiB are used for selecting the bit line 34, not the sub-word line 32.
Compared with the device of FIG. 2, the device of FIG. 3 does not increase the area required for decoding the row address but has a disadvantage in that the number of memory cells to be sensed increases. In the memory cell array shown in FIG. 3, when one of the sub-word lines 32 is selected by the pre-word line signal PW and the signal PX, 2n bit lines 34 connected to the selected sub-word line 32 are activated. At this time, the group select signals RAi and RAiB are applied to a column decoder (not shown) so that either a bit line 34 in the upper memory cell group 30b or a bit line 34 in the lower memory cell group 30a is selected.
When the sub-word line 32 is activated and data in memory cells are transmitted to the 2n bit lines 34, 2n sense amplifiers 38a and 38b perform sensing operation with respect to the data in the 2n bit lines in response to a signal for driving the sense amplifiers 38a and 38b. In this case, while a bit line 34 in the upper memory cell group 30b is selected by a column address and the group select signal RAiB, no operation such as read or write is performed in the memory cells of the lower memory cell group 30a. However, data in the memory cells in the lower memory cell group 30a are still restored by the sense amplifiers 38a and 38b because the sub-word line 32 connected to the 2n bit lines of the upper and low memory cell groups 36b and 36a is selected. As a result, unnecessary sensing operation is performed in the lower memory cell group 30a. This causes sensing noise and sensing current to increase. In a like manner, such unnecessary sensing operation also occurs in the upper memory cell group 30b, when the lower memory cell group 30a is selected by the group select signal RAi.